(1) Field of the Invention
The invention relates to the field of semiconductor manufacturing, and more specifically to a novel method of performing NWELL and PWELL implantation that avoids decreasing the breakdown voltage for high voltage devices.
(2) Description of the Prior Art
The rapid evolution of integrated circuits imposes on the semiconductor industry the necessity of creating an efficient and reliable process to separate active devices that function on the current miniaturized scale is. Semiconductor devices are being formed on the silicon substrates of integrated circuits at increasingly higher device densities and smaller feature sizes. The rapid process of device miniaturization and the therefrom following increased density of semiconductor devices presenting new problems of semiconductor device design and manufacturing.
In a CMOS type semiconductor device, one of the devices is formed in either a p-well region or in an n-well region. Single well structures have the disadvantage that impurity concentration in the well region is too high resulting in a decrease of the device operating speed. For high speed operating devices, it is therefore required that the device is fabricated having a twin well structure whereby both p-well and n-well regions are formed in the substrate and both well regions have low impurity concentrations. Optimizing impurity concentrations for the n and p-well regions must in this case optimize device performance.
During operation of a CMOS device, a latch-up occurs in the CMOS device during which a parasitic thyristor is turned on that is derived from the structure of the CMOS device. This occurrence causes an excessive amount of current to flow through the CMOS device causing rapid detonation of device operation to the point where device damage or destruction can occur. To reduce the possibility of this CMOS device thyristor effect, a retrograde well structure is often employed where a well layer has a deep region that has an impurity concentration that is higher than other regions of impurity concentrations. This approach in effect controls the resistance in the deep well region thereby reducing the thyristor switch on effect.
CMOS devices created with micron and sub-micron device features are subject to problems of source to drain region punch-through (most notably occurring in short channel MOSFET devices), the above indicated latch-up of a CMOS device in addition to degradation of insulating characteristics due to punch-through between devices. The problem of source/drain punch-through has typically been resolved by performing a punch-through-stop ion implantation in the device substrate prior to the formation of the CMOS device gate electrode. This ion implant is performed prior to forming the field oxide for the gate electrode.
The indicated processing steps of ion implantation significantly add to the device fabrication complexity and cost. Device performance can also be degraded due to such phenomenon as increased impurity concentration in MOSFET channel regions, reduced carrier mobility due to higher carrier concentrations in critical device regions, increased junction capacitance, the encroachment of impurities from the field regions to the active regions of the device and increased threshold voltage of the device.
To isolate individual devices when creating MOS type circuits, the threshold voltage for the field-oxide areas must be high. To establish this high threshold voltage, special isolation techniques are applied, among these isolation techniques are the LOCOS process, polybuffered LOCOS and shallow trench isolation.
The most widely used method for creating isolation in NMOS and PMOS integrated circuits is the basic LOCOS structure. In the LOCOS approach, a layer of oxide is selectively grown over the field regions of the IC. This is done by covering the active regions with a thin layer of silicon nitride. When the field oxide is grown, the active regions remain covered by nitride, which prevents oxidation of the silicon beneath. In the field regions the surface of the silicon substrate is exposed prior to field oxidation by etching away the nitride layers in these areas. In addition, the silicon in these regions is also selectively implanted at this point with the channel-stop dopant. Thus, the channel-stop regions become self-aligned to the field oxide.
If the field oxide is selectively grown without etching the silicon, the resulting field oxide will be partially recessed. If, on the other hand, the silicon is etched after the oxide-preventing layer is patterned, the field oxide can be grown until it forms a planar surface with the silicon substrate. This is known as the fully recessed isolation oxide process. In the semi-recessed process, the height of the oxide protruding above the level of the active region surface is larger than in the fully recessed process, but it is smaller than in the grow-oxide-and-etch process. In addition, the semi-recessed oxide step has a gentle slope that is more easily covered by subsequent polysilicon and metal layers.
The conventional LOCOS isolation process has a problem known as "bird's beak encroachment" and is therefore limited to a scalability within about the 1 um range.
The LOCOS process than uses the property that oxygen diffuses through Si.sub.3 N.sub.4 very slowly. When silicon is covered with silicon nitride no oxide can grow. In addition, nitride itself oxidizes at a very slow rate and will thus remain as an integral oxidation barrier layer throughout the entire oxidation step.
FIGS. 1 through 3 show Prior Art LOCOS processing steps.
FIG. 1 shows, how, after a wafer 10 with a bare silicon surface is cleaned, a 20 to 60 nm. layer 12 of SiO.sub.2 is thermally grown on its surface. Next, a 100 to 200 nm.-thick layer 14 of Chemical Vapor Deposition (CVD) silicon nitride Si.sub.3 Ni.sub.4, which functions as an oxidation mask, is deposited. The active regions are then defined with a photolithographic step so that they are protected by the photoresist patterns. The composite oxide/nitride layers are then plasma-etched as a stack. With the photoresist pattern in place, the wafer is subsequently implanted with a 10.sup.12 to 10.sup.13 cm.sup.-2 dose of boron with energies in the range of 60 to 100 keV. This channel stop is now self-aligned to the n-channel devices. The underlying layer of oxide within the stack, called a pad or buffer oxide, is used to cushion the transition of stresses between the silicon substrate and the nitride film.
FIG. 2 shows how, after the channel stop implant, the field oxide 20 with a thickness of 400 to 900 nm. is thermally grown by wet oxidation at temperatures of 900 to 1000 degrees C. for 4 to 8 hours.
FIG. 3 shows the next stage of the processing sequence, the masking nitride layer is stripped with phosphoric acid at 180 degrees C. using a reflux boiler. Then the pad oxide is etched (not shown).
Another method used for establishing device isolation is the use of Shallow Trench Isolation (STI). STI can be made using a variety of methods. For instance, one method is the Buried Oxide (BOX) isolation used for shallow trenches. The method involves filling the trenches with a chemical vapor deposition (CVD) silicon oxide (SiO.sub.2) and then etched back or mechanically/chemically polished to yield a planar surface. The shallow trenches etched for the BOX process are anisotropically plasma etched into the silicon substrate and are typically between 0.3 and 0.8 micrometer (um.) deep. STI are formed around the active device to a depth between 3000 and 20000 Angstrom.
A further consideration in forming CMOS devices is how the substrates will be formed for the two types of transistors. For n-channel type transistors, a p-substrate is required while for p-type transistor an n-substrate is required. This leads to three different approaches in forming the two different types of substrates, that is the p-well, n-well and twin-well approach.
For the n-well process, an n-well is formed in a p-type substrate. This process involves implanting an n-type dopant into a p-substrate whereby the dopant concentration must be high and high enough that the p-substrate is overcompensated such that good control of the n-type doping is achieved. This assures that, because the concentration of the p-substrate dopant is high, the device characteristics can be well established for the n-channel device. In order to assure this control, the n-well dopant typically is in the order of five to ten times higher than that of the p-substrate. This extreme level of doping however has negative effects in the p-channel transistor due to the extreme concentration of dopant. These negative effects include increased back-gate bias sensitivity, reduction of molecular mobility and increased internal device capacitance.
A process similar to the process described above for the n-well can be applied to create the p-well. The p-well created in this similar manner also suffers the negative effects of the p-well overcompensating of the n-substrate as a consequence of which the n-channel transistor suffers from excessive doping effects.
FIG. 4 gives an overview of a MOSFET device. The process of creating a MOSFET device starts with the surface of a semiconductor substrate 10, FIG. 4. Forming insulation regions that bound the active region isolates the active region that is to be used for the creation of the gate electrode. Field Oxide (FOX) isolation regions 12 can be used to electrically isolate the device. A thin layer of gate oxide is grown over the surface of the substrate 10 on the active device region. To create the gate structure, a layer of polysilicon is grown over the thin layer of gate oxide. The polysilicon layer is masked and the exposed polysilicon and the thin layer of oxide are etched to create the polysilicon gate 14 that is separated from the substrate by the remaining thin layer of oxide 16. The doping of the source/drain regions starts with creating the lightly N.sup.+ doped diffusion (LDD) regions 32/34. The sidewall spacers 22 for the gate structure are formed after which the source and drain region doping is completed by doping the source/drain regions 18/20 to the desired level of conductivity using a N.sup.+ dopant.
Contact points to the source/drain regions and the electrode gate are then formed by first selectively depositing a layer of titanium over the surface of the source/drain regions and the top surface of the gate electrode. This titanium is annealed causing the deposited titanium to react with the underlying silicon of the source/gain regions and the doped surface of the gate electrode. This anneal forms layers of titanium silicide 24/26 on the surfaces of the source/drain regions and layer 28 on the top surface of the gate electrode.
The metal contacts with the source/drain regions and the gate electrode are formed as a final step. A dielectric 30 such as silicon oxide is blanket deposited over the surface of the created structure, patterned and etched to create contact openings 36/37 over the source/drain regions and opening 38 over the top surface of the gate electrode. The metalization layer selectively deposited over the patterned dielectric establishes the electrical contacts 40/42 with the source/drain regions and 44 with the top surface of the gate electrode.
Using conventional implantation processes, the p-field implant is performed simultaneously into the active region and into the device isolation (field) region of the device. This approach decreases the breakdown voltage of the device since the p-field implant at the interface between the source/drain junction and the LOCOS (field oxide) region increases the well concentration of the junction edge resulting in a decrease of the breakdown voltage of the device.
For future processing step of p-field implant, these two simultaneous processing steps of implant are divided into two separate steps of implantation, that is a retrograde implant is first used for the device p-field well implant while device STI is used for device isolation.
U.S. Pat. No. 5,866,458 (Lee) shows a CMOS device with N and P regions under a FOX.
U.S. Pat. No. 5,821,589 (Borland) and U.S. Pat. No. 5,501,993 (Borland) disclose several cluster I/I under FOX regions.
U.S. Pat. No. 5,693,505 (Kobayashi) shows a method that I/I several regions and wells under FOX's.
U.S. Pat. No. 5,393,679 (Yang) teaches a double charge I/I for a retrograde process.